W83759A
AC Characteristics, continued
SYMBOL
PARAMETER
MIN.
MAX.
18
UNIT
FIG.
Fig. 4, 5
Fig. 4, 5
Fig. 4, 5
t19
t20
t21
IDEA[2:0] Valid Delay from Address Valid
-
5
-
nS
nS
nS
IDEA[2:0] Invalid Delay from Address Change
18
18
IDE0CS0 , IDE1CS0 Valid Delay from
Address valid
t22
5
18
nS
Fig. 4, 5
IDE0CS0 , IDE1CS0 Invalid Delay from
Address Change
t23
t24
-
-
22
24
nS
nS
Fig. 4, 5
Fig. 4, 5
IDEIOR, IDEIOW Active Delay from LCLK
IDEIOR, IDEIOW Inactive Delay from LCLK
IDE Read IDD Data Hold Time from LCLK
IDE Read IDD to HD Delay
IDE Read HD Float Delay from LCLK
IDE Write IDD Drive Delay
IDE Write IDD Float Delay
IDEA[2:0] Valid Delay from A2 SA[1:0] Valid
IDEA[2:0] Invalid Delay from A2 SA[1:0]
Change
t25
t26
t27
t28
t29
t30
t31
0
-
10
-
10
-
5
-
nS
nS
nS
nS
nS
nS
nS
Fig. 4
Fig. 4
Fig. 4
Fig. 5
Fig. 5
Fig. 6, 7
Fig. 6, 7
16
30
20
30
20
20
t32
t33
-
17
17
nS
nS
Fig. 6, 7
Fig. 6, 7
IDE0CS1, IDE1CS1 Valid Delay from Address
Valid
4
IDE0CS1, IDE1CS1 Invalid Delay from
Address Change
t34
t35
ISA IDE Read IDD to SD Delay
ISA IDE Read IDD Data Hold Time from
IDEIOR
8
5
18
-
nS
nS
Fig. 6
Fig. 6
t36
t37
ISA IDE Write SD to IDD Delay
ISA IDE Wrtie SD Data Hold Time from
XIOW
8
30
18
-
nS
nS
Fig. 7
Fig. 7
t38
t39
VGA Read IDD to HD Delay
-
-
16
20
nS
nS
Fig. 8
Fig. 8
VGA Read HD Float Delay from VGAOEL
VGA Write HD to IDD Delay
t40
t41
-
-
16
20
nS
nS
Fig. 9
Fig. 9
VGA Write HD Float Delay from VGAOEH
t42
t43
t44
t45
-
-
-
-
20
20
20
20
nS
nS
nS
nS
Fig. 6
Fig. 6
Fig. 7
Fig. 7
ISA IDD Read IDEIOR Active Delay from
XIOR
ISA IDD Read IDEIOR Inactive Delay from
XIOR
ISA IDE Write IDEIOW Active Delay from
XIOW
ISA IDE Write IDEIOW Inactive Delay from
XIOW
- 34 -
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