W83627HF/ F/ HG/ G
9.8
Logical Device 6 （CIR）
CR30 （Default 0x00）
BIT
DESCRIPTION
7 - 1
0
Reserved.
Logic device activation control
1： Active
0： Inactived
CR60, CR 61 （Default 0x00, 0x00）
These two registers select CIR I/O base address [0x100：0xFF8] on 8 byte boundary.
CR70 （Default 0x00）
BIT
7 - 4
3 - 0
DESCRIPTION
Reserved.
These bits select IRQ resource for CIR.
9.9
Logical Device 7 （Game Port, MIDI Port and GPIO Port 1）
CR30 （Default 0x00）
BIT
DESCRIPTION
7 - 3
2
Reserved
MIDI Port activation control
1： Enable（MIDI Port will be active individually even though CR30[0] is set “0”）
0： Disbale
1
0
Game Port activation control
1： Enable（Game Port will be active individually even though CR30[0] is set “0”）
0： Disable
Logic device activation control
1： Active
0： Inactived
CR60, CR 61 （Default 0x02, 0x01 if PNPCVS = 0 during POR, default 0x00 otherwise）
These two registers select the Game Port base address [0x100：0xFFF] on 1 byte boundary.
CR62, CR 63 （Default 0x03, 0x30 if PNPCVS = 0 during POR, default 0x00 otherwise）
These two registers select the MIDI Port base address [0x100：0xFFF] on 2 byte boundary.
Publication Release Date: June 09, 2006
- 97 -
Revision 2.27
WINBOND [ WINBOND ]
