W83627HF/ F/ HG/ G
9.6
Logical Device 3 （UART B）
CR30 （Default 0x01 if PNPCVS = 0 during POR, default 0x00 otherwise）
BIT
7 - 1
0
DESCRIPTION
Reserved.
Logic device activation control
1： Active
0： Inactived
CR60, CR 61 （Default 0x02, 0xF8 if PNPCVS = 0 during POR, default 0x00, 0x00 otherwise）
These two registers select Serial Port 2 I/O base address [0x100：0xFF8] on 8 byte boundary.
CR70 （Default 0x03 if PNPCVS = 0 during POR, default 0x00 otherwise）
BIT
7 - 4
3 - 0
DESCRIPTION
Reserved.
These bits select IRQ resource for Serial Port 2.
CRF0 （Default 0x00）
BIT
DESCRIPTION
7 - 4
3
Reserved.
RXW4C
0： No reception delay when IR is changed from TX mode to RX mode.
1： Reception delays 4 characters time （40 bit-time） when SIR is changed from TX
mode to RX mode.
TXW4C
2
0： No transmission delay when SIR is changed from RX mode to TX mode.
1： Transmission delays 4 characters time （40 bit-time） when SIR is changed from
RX mode to TX mode.
1 - 0
SUBCLKB1, SUBCLKB0
00： UART B clock source is 1.8462 Mhz （24MHz/13）
01： UART B clock source is 2 Mhz （24MHz/12）
10： UART B clock source is 24 Mhz （24MHz/1）
11： UART B clock source is 14.769 Mhz （24mhz/1.625）
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