W83627HF/ F/ HG/ G
9.5
Logical Device 2 （UART A）
CR30 （Default 0x01 if PNPCVS = 0 during POR, default 0x00 otherwise）
BIT
7 - 1
0
DESCRIPTION
Reserved.
Logic device activation control
1： Active
0： Inactived
CR60, CR 61 （Default 0x03, 0xF8 if PNPCVS = 0 during POR, default 0x00, 0x00 otherwise）
These two registers select Serial Port 1 I/O base address [0x100：0xFF8] on 8 byte boundary.
CR70 （Default 0x04 if PNPCVS = 0 during POR, default 0x00 otherwise）
BIT
7 - 4
3 - 0
DESCRIPTION
Reserved.
These bits select IRQ resource for Serial Port 1.
CRF0 （Default 0x00）
BIT
DESCRIPTION
7 - 2
1 - 0
Reserved.
SUACLKB1, SUACLKB0
00： UART A clock source is 1.8462 Mhz （24MHz/13）
01： UART A clock source is 2 Mhz （24MHz/12）
10： UART A clock source is 24 Mhz （24MHz/1）
11： UART A clock source is 14.769 Mhz （24mhz/1.625）
Publication Release Date: June 09, 2006
Revision 2.27
- 93 -
WINBOND [ WINBOND ]
