W25M02GV
8.2.8 Bad Block Management (A1h)
Due to large NAND memory density size and the technology limitation, NAND memory devices are
allowed to be shipped to the end customers with certain amount of “Bad Blocks” found in the factory
testing. Up to 2% of the memory blocks can be marked as “Bad Blocks” upon shipment, which is a
maximum of 20 blocks for each of the stacked W25N01GV die. In order to identify these bad blocks, it is
recommended to scan the entire memory array for bad block markers set in the factory. A “Bad Block
Marker” is a non-FFh data byte stored at Byte 0 of Page 0 for each bad block. An additional marker is also
stored in the first byte of the 64-Byte spare area.
W25M02GV offers a convenient method to manage the bad blocks typically found in NAND flash memory
after extensive use. The “Bad Block Management” command is initiated by shifting the instruction code
“A1h” into the DI pin and followed by the 16-bit “Logical Block Address” and 16-bit “Physical Block
Address” as illustrated in Figure 11. The logical block address is the address for the “bad” block that will
be replaced by the “good” block indicated by the physical block address.
Once a Bad Block Management command is successfully executed, the specified LBA-PBA link will be
added to the internal Look Up Table (LUT). Up to 20 links can be established in the non-volatile LUT. If all
20 links have been written, the LUT-F bit in the Status Register will become a 1, and no more LBA-PBA
links can be established. Therefore, prior to issuing the Bad Block Management command, the LUT-F bit
value can be checked or a “Read BBM Look Up Table” command can be issued to confirm if spare links
are still available in the LUT.
Figure 11. Bad Block Management Instruction
Publication Release Date: July 1, 2015
- 32 -
Preliminary - Revision B
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