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25M02GVTCIG 参数 Datasheet PDF下载

25M02GVTCIG图片预览
型号: 25M02GVTCIG
PDF下载: 下载PDF文件 查看货源
内容描述: [3V 2G-BIT (2 x 1G-BIT) SERIAL SLC NAND FLASH MEMORY WITH DUAL/QUAD SPI BUFFER READ & CONTINUOUS READ CONCURRENT OPERATIONS]
分类和应用:
文件页数/大小: 68 页 / 820 K
品牌: WINBOND [ WINBOND ]
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W25M02GV  
8.2.6 Write Enable (06h)  
The Write Enable instruction (Figure 9) sets the Write Enable Latch (WEL) bit in the Status Register to a  
1. The WEL bit must be set prior to every Page Program, Quad Page Program and Block Erase  
instruction. The Write Enable instruction is entered by driving /CS low, shifting the instruction code “06h”  
into the Data Input (DI) pin on the rising edge of CLK, and then driving /CS high.  
/CS  
Mode 3  
Mode 0  
0
1
2
3
4
5
6
7
Mode 3  
Mode 0  
CLK  
Instruction (06h)  
DI  
(IO0)  
High Impedance  
DO  
(IO1)  
Figure 9. Write Enable Instruction  
8.2.7 Write Disable (04h)  
The Write Disable instruction (Figure 10) resets the Write Enable Latch (WEL) bit in the Status Register to  
a 0. The Write Disable instruction is entered by driving /CS low, shifting the instruction code “04h” into the  
DI pin and then driving /CS high. Note that the WEL bit is automatically reset after Power-up and upon  
completion of the Page Program, Quad Page Program, Block Erase and Reset instructions.  
/CS  
Mode 3  
Mode 0  
0
1
2
3
4
5
6
7
Mode 3  
Mode 0  
CLK  
Instruction (04h)  
DI  
(IO0)  
High Impedance  
DO  
(IO1)  
Figure 10. Write Disable Instruction  
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