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25M02GVTCIG 参数 Datasheet PDF下载

25M02GVTCIG图片预览
型号: 25M02GVTCIG
PDF下载: 下载PDF文件 查看货源
内容描述: [3V 2G-BIT (2 x 1G-BIT) SERIAL SLC NAND FLASH MEMORY WITH DUAL/QUAD SPI BUFFER READ & CONTINUOUS READ CONCURRENT OPERATIONS]
分类和应用:
文件页数/大小: 68 页 / 820 K
品牌: WINBOND [ WINBOND ]
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W25M02GV  
8.2.12 Load Program Data (02h) / Random Load Program Data (84h)  
The Program operation allows from one byte to 2,112 bytes (a page) of data to be programmed at  
previously erased (FFh) memory locations. A Program operation involves two steps: 1. Load the program  
data into the Data Buffer. 2. Issue “Program Execute” command to transfer the data from Data Buffer to  
the specified memory page.  
A Write Enable instruction must be executed before the device will accept the Load Program Data  
Instructions (Status Register bit WEL= 1). The “Load Program Data” or “Random Load Program Data”  
instruction is initiated by driving the /CS pin low then shifting the instruction code “02h” or “84h” followed by  
a 16-bit column address (only CA[11:0] is effective) and at least one byte of data into the DI pin. The /CS  
pin must be held low for the entire length of the instruction while data is being sent to the device. If the  
number of data bytes sent to the device exceeds the number of data bytes in the Data Buffer, the extra  
data will be ignored by the device. The Load Program Data instruction sequence is shown in Figure 15.  
Both “Load Program Data” and “Random Load Program Data” instructions share the same command  
sequence. The difference is that “Load Program Data” instruction will reset the unused the data bytes in  
the Data Buffer to FFh value, while “Random Load Program Data” instruction will only update the data  
bytes that are specified by the command input sequence, the rest of the Data Buffer will remain  
unchanged.  
If internal ECC algorithm is enabled, all 2,112 bytes of data will be accepted, but the bytes designated for  
ECC parity bits in the extra 64 bytes section will be overwritten by the ECC calculation. If the ECC-E bit is  
set to a 0 to disable the internal ECC, the extra 64 bytes section can be used for external ECC purpose or  
other usage.  
/CS  
Mode 3  
Mode 0  
0
7
8
9
21 22 23 24  
CLK  
Instruction  
Column Address[15:0]  
15 14 13  
DI  
(IO0)  
2
1
0
7
02h / 84h  
High Impedance  
DO  
(IO1)  
/CS  
24  
30 31 32  
38 39 40  
Mode 3  
Mode 0  
CLK  
Data-0  
Data-1  
Data-2111  
DI  
(IO0)  
7
6
1
0
7
6
1
0
7
0
7
6
1
0
High Impedance  
DO  
(IO1)  
Figure 15. Load / Random Load Program Data Instruction  
Publication Release Date: July 1, 2015  
Preliminary - Revision B  
- 36 -  
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