WCSN0436V1P
Switching Characteristics Over the Operating Range[13, 14, 15]
-166
-150
-143
-133
-100
-80
Parameter
tCYC
Description
Clock Cycle Time
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
5.0
1.4
1.4
1.5
6.6
2.5
2.5
1.5
7.0
2.8
2.8
2.0
7.5
3.0
3.0
2.0
10
4.0
4.0
2.2
12.5
4.0
4.0
2.5
ns
ns
ns
ns
tCH
Clock HIGH
Clock LOW
tCL
tAS
Address Set-Up Before CLK
Rise
tAH
tCO
Address Hold After CLK Rise
0.5
0.5
0.5
0.5
0.5
1.0
ns
ns
Data Output Valid After CLK
Rise
3.5
3.8
4.0
4.2
5.0
7.0
tDOH
Data Output Hold After CLK
Rise
1.5
1.5
1.5
1.5
1.5
ns
tCENS
tCENH
tWES
CEN Set-Up Before CLK Rise 1.5
1.5
0.5
1.5
2.0
0.5
2.0
2.0
0.5
2.0
2.2
0.5
2.2
2.5
1.0
2.5
ns
ns
ns
CEN Hold After CLK Rise
0.5
1.5
GW, BWS[3:0] Set-Up Before
CLK Rise
tWEH
tALS
GW, BWS[3:0] Hold After CLK 0.5
Rise
0.5
1.5
0.5
2.0
0.5
2.0
0.5
2.2
1.0
2.5
ns
ns
ADV/LD Set-Up Before CLK
Rise
1.5
tALH
tDS
ADV/LD Hold after CLK Rise
0.5
0.5
1.5
0.5
1.7
0.5
1.7
0.5
2.0
1.0
2.5
ns
ns
Data Input Set-Up Before CLK 1.5
Rise
tDH
Data Input Hold After CLK Rise 0.5
0.5
1.5
0.5
2.0
0.5
2.0
0.5
2.2
1.0
2.5
ns
ns
tCES
Chip Enable Set-Up Before
CLK Rise
1.5
tCEH
Chip Enable Hold After CLK
Rise
0.5
0.5
0.5
0.5
0.5
1.0
ns
tCHZ
tCLZ
Clock to High-Z[12, 14, 15, 16]
Clock to Low-Z[12, 14, 15, 16]
1.5 3.2 1.5 3.2 1.5 3.5 1.5 3.5 1.5 3.5 1.5 5.0
ns
ns
ns
1.5
1.5
0
1.5
0
1.5
0
1.5
0
1.5
0
tEOHZ
OE HIGH to Output High-Z[12,
3.0
3.0
4.0
4.2
5.0
7.0
14, 15, 16]
tEOLZ
OE LOW to Output Low-Z[12,
0.0
ns
ns
14, 15, 16]
tEOV
OE LOW to Output Valid[14]
3.2
3.5
4.0
4.2
5.0
7.0
Notes:
14.
tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with A/C test conditions shown in part (a) of AC Test Loads. Transition is measured ± 200 mV from steady-state
voltage.
15. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
16. This parameter is sampled and not 100% tested.
Document #: 38-05246 Rev. **
Page 9 of 14
WEIDA [ WEIDA SEMICONDUCTOR, INC. ]
