WCSN0436V1P
and DP[3:0] are automatically three-stated during the data por-
tion of a write cycle, regardless of the state of OE.
Linear Burst Sequence
Burst Write Accesses
First
Address
Second
Address
Third
Address
Fourth
Address
The WCSN0436V1p has an on-chip burst counter that allows
the user the ability to supply a single address and conduct up
to four WRITE operations without reasserting the address in-
puts. ADV/LD must be driven LOW in order to load the initial
address, as described in the Single Write Access section
above. When ADV/LD is driven HIGH on the subsequent clock
rise, the chip enables (CE1, CE2, and CE3) and WE inputs are
ignored and the burst counter is incremented. The correct
BWS[3:0] inputs must be driven in each cycle of the burst write
in order to write the correct bytes of data.
Ax+1, Ax
Ax+1, Ax
Ax+1, Ax
Ax+1, Ax
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Interleaved Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
Ax+1, Ax
Ax+1, Ax
Ax+1, Ax
Ax+1, Ax
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
[
]
Cycle Description Truth Table 1, 2, 3, 4, 5, 6
Address
Used
ADV/
LD/
Operation
CE
CEN
WE
BWSx
CLK
Comments
Deselected
External
1
0
L
X
X
L-H
I/Os three-state following next rec-
ognized clock.
Suspend
-
X
1
X
X
X
L-H
Clock ignored, all operations sus-
pended.
Begin Read
Begin Write
External
External
0
0
0
0
0
0
1
0
X
L-H
L-H
Address latched.
Valid
Address latched, data presented
two valid clocks later.
Burst Read
Operation
Internal
X
0
1
X
X
L-H
Burst Read operation. Previous ac-
cess was a Read operation. Ad-
dresses incremented internally in
conjunction with the state of
MODE.
Burst Write
Operation
Internal
X
0
1
X
Valid
L-H
Burst Write operation. Previous ac-
cess was a Write operation. Ad-
dresses incremented internally in
conjunction with the state of
MODE. Bytes written are deter-
mined by BWS[3:0]
.
Notes:
1. X=”Don't Care”, 1=Logic HIGH, 0=Logic LOW, CE stands for ALL Chip Enables active. BWS = 0 signifies at least one Byte Write Select is active, BWS
=
x
x
Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE and BWS
3. The DQ and DP pins are controlled by the current cycle and the OE signal.
4. CEN=1 inserts wait states.
5. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
6. OE assumed LOW.
. See Write Cycle Description table for details.
[3:0]
Document #: 38-05246 Rev. **
Page 5 of 14
WEIDA [ WEIDA SEMICONDUCTOR, INC. ]
