WCSN0436V1P
Switching Waveforms (continued)
Burst Sequences
CLK
tCYC
tALH
tALS
ADV/LD
tCL
tCH
tAH
tAS
RA1
WA2
ADDRESS
WE
RA3
tWS
tWH
tWS
tWH
BWS[3:0]
tCES
tCEH
CE
tCLZ
tCHZ
tDH
tDOH
tCLZ
Q3
Out
Data-
In/Out
Q1
Q1+2
Out
Q1+3
Out
D2
In
D2+2
In
D2+3
In
Q1+1
Out
D2+1
In
Out
Device
originally
deselected
tCO
tCO
tDS
The combination of WE & BWS[3:0] define a write cycle (see Write Cycle Description table).
CE is the combination of CE1, CE2, and CE3. All chip enables need to be active in order to select
the device. Any chip enable can deselect the device. RAx stands for Read Address X, WA stands for
Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. CEN held
LOW. During burst writes, byte writes can be conducted by asserting the appropriate BWS[3:0] input signals.
Burst order determined by the state of the MODE input. CEN held LOW. OE held LOW.
= UNDEFINED
= DON’T CARE
Document #: 38-05246 Rev. **
Page 11 of 14
WEIDA [ WEIDA SEMICONDUCTOR, INC. ]
