WCSN0436V1P
Pin Definitions
(continued)
Pin Number
5, 10, 17, 21,
26, 40, 55, 60,
64, 67, 71, 76,
90
83, 84
Name
V
SS
I/O
Ground
Description
Ground for the device. Should be connected to ground of the system.
NC
-
-
No connects. Reserved for address inputs for depth expansion. Pin 83 and 84 will
be used for 256K and 512K depths respectively.
Do Not Use pins. These pins should be left floating or tied to V
SS
.
Burst Read Accesses
The WCSN036V1p has an on-chip burst counter that allows
the user the ability to supply a single address and conduct up
to four Reads without reasserting the address inputs. ADV/LD
must be driven LOW in order to load a new address into the
SRAM, as described in the Single Read Access section above.
The sequence of the burst counter is determined by the MODE
input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A0 and A1 in the burst sequence, and will
wrap-around when incremented sufficiently. A HIGH input on
ADV/LD will increment the internal burst counter regardless of
the state of chip enables inputs or WE. WE is latched at the
beginning of a burst cycle. Therefore, the type of access (Read
or Write) is maintained throughout the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
1
, CE
2
,
and CE
3
are ALL asserted active, and (3) the write signal WE
is asserted LOW. The address presented to A
0
−A
16
is loaded
into the Address Register. The write signals are latched into
the Control Logic block.
On the subsequent clock rise the data lines are automatically
three-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ
[31:0]
and
DP
[3:0]
. In addition, the address for the subsequent access
(Read/Write/Deselect) is latched into the Address Register
(provided the appropriate control signals are asserted).
On the next clock rise the data presented to DQ
[31:0]
and
DP
[3:0]
(or a subset for byte write operations, see Write Cycle
Description table for details) inputs is latched into the device
and the write is complete.
The data written during the Write operation is controlled by
BWS
[3:0]
signals. The WCSN0436V1P provides byte write ca-
pability that is described in the Write Cycle Description table.
Asserting the Write Enable input (WE) with the selected Byte
Write Select (BWS
[3:0]
) input will selectively write to only the
desired bytes. Bytes not selected during a byte write operation
will remain unaltered. A synchronous self-timed write mecha-
nism has been provided to simplify the write operations. Byte
write capability has been included in order to greatly simplify
Read/Modify/Write sequences, which can be reduced to sim-
ple byte write operations.
Because the WCSN0436V1P is a common I/O device, data
should not be driven into the device while the outputs are ac-
tive. The Output Enable (OE) can be deasserted HIGH before
presenting data to the DQ
[31:0]
and DP
[3:0]
inputs. Doing so will
three-state the output drivers. As a safety precaution, DQ
[31:0]
38, 39, 42, 43 DNU
Introduction
Functional Overview
The WCSN0436V1P is a synchronous-pipelined Burst SRAM
designed specifically to eliminate wait states during
Write/Read transitions. All synchronous inputs pass through
input registers controlled by the rising edge of the clock. The
clock signal is qualified with the Clock Enable input signal
(CEN). If CEN is HIGH, the clock signal is not recognized and
all internal states are maintained. All synchronous operations
are qualified with CEN. All data outputs pass through output
registers controlled by the rising edge of the clock. Maximum
access delay from the clock rise (t
CO
) is 3.5 ns (166-MHz de-
vice).
Accesses can be initiated by asserting all three Chip Enables
(CE
1
, CE
2
, CE
3
) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The ac-
cess can either be a read or write operation, depending on the
status of the Write Enable (WE). BWS
[3:0]
can be used to con-
duct byte write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been de-
selected in order to load a new address for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
1
, CE
2
,
and CE
3
are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and (4) ADV/LD is asserted
LOW. The address presented to the address inputs (A
0
−A
16
)
is latched into the Address Register and presented to the
memory core and control logic. The control logic determines
that a read access is in progress and allows the requested
data to propagate to the input of the output register. At the
rising edge of the next clock the requested data is allowed to
propagate through the output register and onto the data bus
within 3.5 ns (166-MHz device) provided OE is active LOW.
After the first clock of the read access the output buffers are
controlled by OE and the internal control logic. OE must be
driven LOW in order for the device to drive out the requested
data. During the second clock, a subsequent operation
(Read/Write/Deselect) can be initiated. Deselecting the device
is also pipelined. Therefore, when the SRAM is deselected at
clock rise by one of the chip enable signals, its output will
three-state following the next clock rise.
Document #: 38-05246 Rev. **
Page 4 of 14
WEIDA [ WEIDA SEMICONDUCTOR, INC. ]
