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WED9LC6816V1312BI 参数 Datasheet PDF下载

WED9LC6816V1312BI图片预览
型号: WED9LC6816V1312BI
PDF下载: 下载PDF文件 查看货源
内容描述: 256Kx32 SSRAM / SDRAM 4Mx32 [256Kx32 SSRAM/4Mx32 SDRAM]
分类和应用: 存储内存集成电路静态存储器动态存储器
文件页数/大小: 27 页 / 1138 K
品牌: WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
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WED9LC6816V  
White Electronic Designs  
SDRAM AC Characteristics  
(Vcc = 3.3V -5% / +10% unless otherwise noted; 0°C Ta 70°C, Commercial; -40°C Ta 85°C, Industrial)  
125MHz  
100MHz  
83MHz  
Min  
Parameter  
Symbol  
tCC  
Min  
Max  
1000  
1000  
6
Min  
Max  
1000  
1000  
7
Max  
1000  
1000  
8
Units  
ns  
Clock Cycle Time (1)  
CL = 3  
CL = 2  
8
10  
12  
12  
15  
tCC  
10  
ns  
Clock to valid Output delay (1,2)  
Output Data Hold Time (2)  
tSAC  
tOH  
ns  
3
3
3
2
1
2
3
3
3
2
1
2
3
3
3
2
1
2
ns  
Clock HIGH Pulse Width (3)  
Clock LOW Pulse Width (3)  
Input Setup Time (3)  
tCH  
ns  
tCL  
ns  
tSS  
ns  
Input Hold Time (3)  
tSH  
ns  
CK# to Output Low-Z (2)  
tSLZ  
tSHZ  
tRRD  
tRCD  
tRP  
ns  
CK# to Output High-Z  
7
7
8
ns  
Row Active to Row Active Delay (4)  
RAS# to CAS# Delay (4)  
20  
20  
20  
50  
70  
70  
1
20  
20  
20  
50  
80  
80  
1
24  
24  
24  
60  
90  
90  
1
ns  
ns  
Row Precharge Time (4)  
ns  
Row Active Time (4)  
tRAS  
tRC  
10,000  
10,000  
10,000  
ns  
Row Cycle Time - Operation (4)  
Row Cycle Time - Auto Refresh (4,8)  
Last Data in to New Column Address Delay (5)  
Last Data in to Row Precharge (5)  
Last Data in to Burst Stop (5)  
Column Address to Column Address Delay (6)  
Number of Valid Output Data (7)  
ns  
tRFC  
tCDL  
tRDL  
tBDL  
tCCD  
ns  
CK#  
CK#  
CK#  
CK#  
1
1
1
1
1
1
1.5  
2
1.5  
2
1.5  
2
ea  
1
2
1
NOTES:  
1. Parameters depend on programmed CAS latency.  
2. If clock rise time is longer than 1ns (trise/2 -0.5)ns should be added to the parameter.  
3. Assumed input rise and fall time = 1ns. If trise of tfall are longer than 1ns. [(trise = tfall)/2] - 1ns should be added to the parameter.  
4. The minimum number of clock cycles required is detemined by dividing the minimum time required by the clock cycle time and then rounding up to the next higher integer.  
5. Minimum delay is required to complete write.  
6. All devices allow every cycle column address changes.  
7. In case of row precharge interrupt, auto precharge and read burst stop.  
8. A new command may be given tRFC after self-refresh exit.  
Contact factory for ordering information.  
White Electronic Designs Corp. reserves the right to change products or specifications without notice.  
September, 2003  
Rev. 1  
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com