WED9LC6816V
White Electronic Designs
SSRAM Operation Truth Table
Operation
Address Used
None
SSCE# SSADS# SSWE# SSOE#
DQ
High-Z
D
Deselected Cycle, Power Down
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
H
L
L
L
X
L
X
X
L
External
External
External
Current
Current
Current
Current
Current
Current
L
L
H
H
H
H
H
H
L
Q
L
L
H
L
High-Z
Q
X
X
H
H
X
H
H
H
H
H
H
H
H
L
High-Z
Q
H
X
X
High-Z
D
D
L
NOTE:
1. X means “don’t care”, H means logic HIGH. L means logic LOW.
2. All inputs except SSOE# must meet setup and hold times around the rising edge (LOW to HIGH) of SSCK.
3. Suspending burst generates wait cycle
4. For a write operation following a read operation, SSOE# must be HIGH before the input data required setup time plus High-Z time
for SSOE# and staying HIGH through out the input data hold time.
5. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
SSRAM Partial Truth Table
Function
SSWE#
BWE0#
BWE1# BWE2# BWE3#
READ
H
X
X
X
X
WRITE one Byte (DQ0-7)
WRITE all Bytes
L
L
L
L
H
L
H
L
H
L
Contact factory for ordering information.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
September, 2003
Rev. 1
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
