W332M72V-XSBX
White Electronic Designs
FIGURE 3 – MODE REGISTER DEFINITION
TABLE 1 – BURST DEFINITION
Order of Accesses Within a Burst
Burst
Length
Starting Column
Address
Type = Sequential Type = Interleaved
A0
0
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
A
12
A
11
A
10
A9
A8
Address Bus
2
4
0-1
1-0
0-1
1-0
1
Mode Register (Mx)
A1
0
A0
0
Reserved*
WB Op Mode CAS Latency BT
Burst Length
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
*Should program
0
1
M12, M11, M10 = 0, 0
to ensure compatibility
with future devices.
Burst Length
1
0
M2 M1M0
M3 = 0
M3 = 1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
1
2
A2
0
A1
0
A0
0
4
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
8
0
0
1
Reserved
Reserved
Reserved
Full Page
Reserved
Reserved
Reserved
Reserved
0
1
0
8
0
1
1
1
0
0
1
0
1
Burst Type
M3
0
1
1
0
Sequential
Interleaved
1
1
1
1
Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
…Cn - 1,
CAS Latency
M6 M5M4
Full
Page
(y)
n = A 0-9
Reserved
Reserved
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Not Supported
(location 0-y)
Cn…
3
NOTES:
Reserved
Reserved
Reserved
Reserved
1. For full-page accesses: y = 1,024.
2. For a burst length of two, A1-9 select the block-of-two burst; A0 selects the starting
column within the block.
3. For a burst length of four, A2-9 select the block-of-four burst; A0-1 select the starting
column within the block.
4. For a burst length of eight, A3-9 select the block-of-eight burst; A0-2 select the
starting column within the block.
M8
0
M7
0
M6-M0
Defined
-
Operating Mode
Standard Operation
-
-
All other states reserved
5. For a full-page burst, the full row is selected and A0-9 select the starting column.
6. Whenever a boundary of the block is reached within a given sequence above, the
following access wraps within the block.
7. For a burst length of one, A0-9 select the unique column to be accessed, and Mode
Register bit M3 is ignored.
Write Burst Mode
M9
0
Programmed Burst Length
Single Location Access
1
Ju;y 2006
Rev. 3
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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