W332M72V-XSBX
White Electronic Designs
32Mx72 Synchronous DRAM
FEATURES
GENERAL DESCRIPTION
ꢀ High Frequency = 100, 125, 133MHz
ꢀ Package:
The 256MByte (2Gb) SDRAM is a high-speed CMOS,
dynamic random-access, memory using 5 chips containing
536,870,912 bits. Each chip is internally configured as a
quad-bank DRAM with a synchronous interface. Each of
the chip’s 134,217,728-bit banks is organized as 8,192
rows by 1,024 columns by 16 bits.
• 208 Plastic Ball Grid Array (PBGA), 16 x 22mm
ꢀ 3.3V ±0.3V power supply for core and I/Os
ꢀ Fully Synchronous; all signals registered on positive
edge of system clock cycle
ꢀ Internal pipelined operation; column address can be
Read and write accesses to the SDRAM are burst ori-
ented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed (BA0, BA1 select the bank; A0-
12 select the row). The address bits registered coincident
with the READ or WRITE command are used to select the
starting column location for the burst access.
changed every clock cycle
ꢀ Internal banks for hiding row access/precharge
ꢀ Programmable Burst length 1,2,4,8 or full page
ꢀ 8192 refresh cycles
ꢀ Commercial, Industrial and Military Temperature
Ranges
ꢀ Organized as 32M x 72
ꢀ Weight: W332M72V-XSBX - 2.0 grams typical
The SDRAM provides for programmable READ or WRITE
burst lengths of 1, 2, 4 or 8 locations, or the full page, with
a burst terminate option.AnAUTO PRECHARGE function
may be enabled to provide a self-timed row precharge that
is initiated at the end of the burst sequence.
BENEFITS
ꢀ 73% SPACE SAVINGS
ꢀ Reduced part count
ꢀ Reduced I/O count
• 23% I/O Reduction
The 2Gb SDRAM uses an internal pipelined architecture to
achieve high-speed operation. This architecture is compatible
with the 2n rule of prefetch architectures, but it also allows
the column address to be changed on every clock cycle to
achieve a high-speed, fully random access. Precharging
one bank while accessing one of the other three banks
will hide the precharge cycles and provide seamless, high-
speed, random-access operation.
ꢀ Reduced trace lengths for lower parasitic
capacitance
ꢀ Suitable for hi-reliability applications
ꢀ Laminate interposer for optimum TCE match
The 2Gb SDRAM is designed to operate at 3.3V. An auto
refresh mode is provided, along with a power-saving,
power-down mode.
* This product is subject to change without notice.
Discrete Approach
ACTUAL SIZE
S
A
V
I
11.9
11.9
11.9
11.9
11.9
16
54
TSOP
54
54
TSOP
54
TSOP
54
TSOP
White Electronic Designs
22.3
TSOP
W332M72V-XSBX
N
G
S
22
Area
5 x 265mm2 = 1325mm2
5 x 54 pins = 270 pins
352mm2
208 Balls
73%
23%
I/O
Count
Ju;y 2006
Rev. 3
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
