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W332M72V-133SBM 参数 Datasheet PDF下载

W332M72V-133SBM图片预览
型号: W332M72V-133SBM
PDF下载: 下载PDF文件 查看货源
内容描述: 32Mx72同步DRAM [32Mx72 Synchronous DRAM]
分类和应用: 存储内存集成电路动态存储器
文件页数/大小: 15 页 / 473 K
品牌: WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
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W332M72V-XSBX  
White Electronic Designs  
FIGURE 4 – CAS LATENCY  
T0  
T1  
T2  
T3  
CLK  
Command  
I/O  
READ  
NOP  
tLZ  
NOP  
tOH  
DOUT  
tAC  
DON'T CARE  
UNDEFINED  
CAS Latency = 2  
T0  
T1  
T2  
T3  
T4  
CLK  
Command  
I/O  
READ  
NOP  
NOP  
tLZ  
NOP  
tOH  
DOUT  
tAC  
CAS Latency = 3  
BURST TYPE  
Accesses within a given burst may be programmed to be  
either sequential or interleaved; this is referred to as the  
burst type and is selected via bit M3.  
OPERATING MODE  
The normal operating mode is selected by setting M7and  
M8 to zero; the other combinations of values for M7 and  
M8 are reserved for future use and/or test modes. The  
programmed burst length applies to both READ and  
WRITE bursts.  
The ordering of accesses within a burst is determined by  
the burst length, the burst type and the starting column  
address, as shown in Table 1.  
Test modes and reserved states should not be used  
because unknown operation or incompatibility with future  
versions may result.  
CAS LATENCY  
The CAS latency is the delay, in clock cycles, between  
the registration of a READ command and the availability  
of the rst piece of output data. The latency can be set to  
two or three clocks.  
TABLE 2 – CAS LATENCY  
ALLOWABLE OPERATING  
FREQUENCY (MHz)  
CAS  
LATENCY = 2  
CAS  
LATENCY = 3  
If a READ command is registered at clock edge n, and the  
latency is m clocks, the data will be available by clock edge  
n+m. The I/Os will start driving as a result of the clock  
edge one cycle earlier (n + m - 1), and provided that the  
relevant access times are met, the data will be valid by  
clock edge n + m. For example, assuming that the clock  
cycle time is such that all relevant access times are met,  
if a READ command is registered at T0 and the latency  
is programmed to two clocks, the I/Os will start driving  
after T1 and the data will be valid by T2. Table 2 below  
indicates the operating frequencies at which each CAS  
latency setting can be used.  
SPEED  
-100  
-125  
-133  
75  
100  
100  
100  
125  
133  
WRITE BURST MODE  
When M9 = 0, the burst length programmed via M0-M2  
applies to both READ and WRITE bursts; when M9 = 1,  
the programmed burst length applies to READ bursts, but  
write accesses are single-location (nonburst) accesses.  
Reserved states should not be used as unknown operation  
or incompatibility with future versions may result.  
Ju;y 2006  
Rev. 3  
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com