SCA8X0/21X0/3100 Series
6.4 Pin Description
1
2
3
4
5
6
12
11
10
9
8
7
Figure 8: Component pinout
Table 12: Component pinout
No.
Name
Type 1)
PD/PU 2)
Function
Connect
1
2
3
4
Reserved
Reserved
AVSS
AVDD
CSB
Not used
Factory use
Negative power supply (analog)
Positive power supply (analog)
Chip select
Gnd
Gnd
Gnd
Vdd
PD
AI
AI
DI
5
PU
CSB
6
7
8
9
10
11
12
MISO
SCK
MOSI
PWM
DVDD
DVSS
EGnd
ZO
DI
DI
ADO
AI
AI
Data output
Serial clock
Data input
Pulse Width Modulation output
Positive power supply (digital)
Negative power supply (digital)
EMC ground
MISO
SCK
MOSI
N.C. or PWM 3)
Vdd
PD
PD
PD
Gnd
Gnd
AI
Notes:
1) A=Analog, D=Digital, I=Input, O=Output, Z=Tristate Output
2) PU=internal pullup, PD=internal pulldown
3) PWM output in some SCA8X0 products, N.C.= Not Connected
6.5 Recommended circuit diagram
Recommended circuit diagram for all product family components with SPI interface is shown in
Figure 9. Following design rules and recommendations should be considered to achieve maximum
performance:
Required:
1
2
3
Connect (C4) 100 nF (ESR < 1) capacitor between AVDD and AVSS
Connect (C5) 100 nF (ESR < 1) capacitor between DVDD and DVSS
Use one power supply VDD for AVDD and DVDD (AVDD voltage level has to
be raised always same time or after DVDD during power up sequence)
Recommended for improved PSRR (Note 1 in Figure 9):
4
5
Connect (C6) 10 µF capacitor between AVDD and AVSS
Connect serial resistance (R1) 10 Ω between VDD and AVDD/DVDD
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