Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
VIS
T7
T1
T5
T6
T9
T10
T0
T2
T3
T4
T8
CLK
tCK2
CKE
Clock min
CS
RAS
CAS
WE
DSF
BS
A8
Address key
A0-A7,
A9,A10
DQM
t
RP
Hi-Z
DQ
Mode Register
Set Command
Any
Command
PrechargeAll
Mode Register Set Cycle (CAS Latency = 1, 2, 3)
The mode register is divided into various fields depending on functionality.
•
Burst Length Field (A2~A0)
This field specifies the data length of column access using the A2~A0 pins and selects the
Burst Length to be 1, 2, 4, 8, or full page.
A2
0
A1
0
A0
0
Burst Length
1
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
Reserved
Reserved
Reserved
Full Page
1
0
1
1
1
0
1
1
1
Document:
Rev.1
Page15
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
