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VG4632321AQ-7 参数 Datasheet PDF下载

VG4632321AQ-7图片预览
型号: VG4632321AQ-7
PDF下载: 下载PDF文件 查看货源
内容描述: 524,288x32x2位CMOS同步图形RAM [524,288x32x2-Bit CMOS Synchronous Graphic RAM]
分类和应用:
文件页数/大小: 81 页 / 1954 K
品牌: VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
 浏览型号VG4632321AQ-7的Datasheet PDF文件第13页浏览型号VG4632321AQ-7的Datasheet PDF文件第14页浏览型号VG4632321AQ-7的Datasheet PDF文件第15页浏览型号VG4632321AQ-7的Datasheet PDF文件第16页浏览型号VG4632321AQ-7的Datasheet PDF文件第18页浏览型号VG4632321AQ-7的Datasheet PDF文件第19页浏览型号VG4632321AQ-7的Datasheet PDF文件第20页浏览型号VG4632321AQ-7的Datasheet PDF文件第21页  
Preliminary  
VG4632321A  
524,288x32x2-Bit  
CMOS Synchronous Graphic RAM  
VIS  
Mode field (A8~A7)  
A7 and A8 must be programmed to “00” in normal operation.  
A8  
0
A7  
0
Test Mode  
normal mode  
0
1
Vendor Use Only  
Vendor Use Only  
1
x
Single Write Mode (A9)  
This bit is used to select the write mode. When the A9 bit is “0”, Burst Read and Burst Write mode is  
selected. When the A9 bit is ”1”, Burst Read and Single Write mode is Selected.  
A9  
0
Single Write Mode  
Burst Read and Burst Write  
Burst Read and Single Write  
1
12 Special Mode Register Set command  
(RAS = ”L”, CAS = ”L”, WE = ”L”, DSF = ”H”, BS, A0-A10 = Register Data)  
The special mode register is used to load the Color and Mask registers, which are used in Block  
Write and masked Write cycles. The control information being written to the Special Mode register is  
applied to the address inputs and the data to be written to either the Color register or the Mask register is  
applied to the DQs. When A6 is “high” during a Special Mode Register Set cycle, the Color register will be  
loaded with the data on the DQs. Similarly, when A5 is “high” during a Special Mode Register Set cycle,  
the Mask register will be loaded with the data on the DQs. A6 = A5 = 1 in the Special Mode Register Set  
cycle is illegal.  
Functions  
Leave Unchanged  
Load Mask Register  
Load Color Register  
Illegal  
BS  
X
A10~A7  
A6  
0
A5  
0
A4~A0  
X
X
X
X
X
X
X
X
X
0
1
X
1
0
X
1
1
One clock cycle is required to complete the write in the Special Mode register. This command can  
be issued at the active state. As in write operation, this command accepts the data needed through DQ  
pins. Therefore it should be attended not to induce bus contention.  
13 No-Operation command  
(RAS = ”H”, CAS = ”H”, WE = ”H”)  
The No-Operation command is used to perform a NOP to SGRAM which is selected (CS is Low).  
This prevents unwanted commands from being registered during idle or wait states.  
14 Burst Stop command  
(RAS = ”H”, CAS = ”H”, WE = ”L’, DSF = ”L”)  
Burst Stop command is used to terminate either fixed-length or full-page bursts. This command is  
only effective in a read/write burst without auto precharge function. The terminated read burst ends after  
a delay equal to the CAS latency (refer to the following figure). The termination of a write burst is shown  
in the following figure.  
Document:  
Rev.1  
Page17  
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