Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
VIS
18
SelfRefresh Exit command (refer to Figure 5 in Timing Waveforms)
(CKE = ”H”, CS = ”H” or CKE = ”H”, RAS = ”H”, CAS = ”H”, WE = ”H”)
The command is used to exit from the SelfRefresh mode. Once this command is registered,
NOP or Device Deselect commands must be issued for tRC(min), because time is required for the
completion of any bank currently being internally refreshed. If auto refresh cycles in bursts are per-
formed during normal operation, a burst of 1024 auto refresh cycles should be completed just prior to
entering, and just after exiting the SelfRefresh mode.
19 Clock Suspend Mode Entry/PowerDown Mode Entry command (refer to Figures 6, 7, and 8 in Timing
Waveforms)
(CKE = ”L”)
When SGRAM operating the burst cycle, the internal CLK is suspended (masked) from the sub-
sequent cycle by issuing this command (asserting CKE ”low”). The device operation is held intact
while CLK is suspended. On the other hand, when both banks are in the idle state, this command per-
forms entry into the PowerDown mode. All input and output buffers (except the CKE buffer) are turned
off in the PowerDown mode. The device may not remain in the Clock Suspend or PowerDown state
longer than the refresh period (16ms) since the command does not perform any refresh operations.
20
Clock Suspend Mode Exit/PowerDown Mode Exit command (refer to Figures 6, 7, and 8 in Timing
Waveforms)
(CKE = ”H”)
When the internal CLK has been suspended, the operation of the internal CLK is resumed from
the subsequent cycle by providing this command (asserting CKE “high”). When the device is in the
PowerDown mode, the device exits this mode and all disabled buffers are turned on to the active
state. tPDE(min.) is required when the device exit from the PowerDown mode. Any subsequent com-
mands can be issued after one clock cycle from the end of this command.
21 Data Write/Output Enable, Data Mask/Output Disable command
(DQM = ”L”, ”H”)
During a write cycle, the DQM signal functions as Data Mask and can control every word of the
input data. During a read cycle, the DQM functions as the control of output buffers. DQM is also used
for device selection, byte selection and bus control in a memory system. DQM0 controls DQ0 to DQ7,
DQM1 controls DQ8 to DQ15, DQM2 controls DQ16 to DQ23, DQM3 controls DQ24 to DQ31, DQM
masks the DQ’s by a byte regardless that the corresponding DQ’s are in a state of write-per-bit mask-
ing or pixel masking. the byte control. The each DQM0-3 corresponds to DQ0-7, DQ8-15, DQ16-23,
DQ24-31.
Document:
Rev.1
Page19
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
