Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
VIS
9
Write and AutoPrecharge command (refer to the following figure)
(RAS = “H” , CAS = “L” , WE = “L” , DSF=”L” , BS = Bank, A8 = ”H”, A0-A7 = Column Address,
A9,A10 = Don’t care)
The Write and AutoPrecharge command performs the precharge operation automatically after
the write operation. Once this command is given, any subsequent command can not occur within a
time delay of {burst length + t
+ t (min.)}. At full-page burst, only write operation is performed in
WR
RP
this command and the auto precharge function is ignored.
T2
T1
T3
T4
T8
T5
T7
T0
T6
CLK
Write A
Auto Precharge
Bank A
Activate
COMMAND
NOP
NOP
NOP
NOP
NOP
NOP
NOP
t
DAL
*
DIN A
DIN A
0
1
CAS latency = 1
t
,DQ’s
ck1
t
DAL
*
CAS latency = 2
DIN A
DIN A
0
1
1
t
,DQ’s
ck2
t
DAL
CAS latency = 3
,DQ’s
*
DIN A
DIN A
0
t
ck3
Begin AutoPrecharge
*
Bank can be reactivated at completion of t
t
= t
+ t
DAL
DAL
WR RP
Burst Write with Auto-Precharge (Burst Length = 2, CAS Latency = 1, 2, 3)
10 Block Write and AutoPrecharge command
(RAS = “H” , CAS = “L” , WE = “H”, DSF = “H” , BS = Bank , A8 = “H” , A3-A7 = Column Address,
A9,A10 = Don’t care DQ0-DQ31 = Column Mask)
The Block Write and AutoPrecharge command performs the precharge operation automatically after
the block write operation. Once this command is given, any subsequent command can not occur within a
time delay of {tBPL + tRP (min.)}.
11 Mode Register Set command
(RAS = “L” , CAS = ”L”, WE = “L” , DSF = “L” , BS , A0-A10 = Register Data)
The mode register stores the data for controlling the various operating modes of SGRAM. The Mode
Register Set command programs the values of CAS latency. Addressing Mode and Burst Length in the
Mode register to make SGRAM useful for variety of different applications. The default values of the Mode
Register after power-up are undefined, therefore this command must be issued at the power-up
sequence. The state of pins A0-A10 and BS in the same cycle is the data written in the mode register.
One clock cycle is required to complete the write in the mode register (refer to the following figure ). The
mode register contents can be changed using the same command and the clock cycle requirements dur-
ing operation as long as both banks are in the idle state.
Document:
Rev.1
Page14
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
