Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
VIS
Figure 18.2. Full Page Read Cycle (Burst Length = Full Page, CAS Latency = 2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
CKE
High
CS
RAS
CAS
WE
DSF
BS
RBy
RBy
RAx
RAx
RBx
RBx
A9
CAx
CBx
A0 ~ A8
DQM
DQ
tRP
Hi-Z
Ax
Ax-2
Ax+1 Ax+2
Ax-1
Bx+5 Bx+6
Bx+2
Bx+4
Ax+1
Bx+1
Bx+3
Ax
Bx
Read
Burst Stop
Command
Activate
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank B
Precharge
Command
Bank B
Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Full Page burst operation does not terminate
when the burst length is satisfied; the burst
counter increments and continues bursting
beginning with the starting address.
Document:
Rev.1
Page41
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
