Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
VIS
Figure19.3 Full Page Write Cycle (Burst Length = Full Page, CAS Latency = 3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK3
CKE
High
CS
RAS
CAS
WE
DSF
BS
RAx
A9
RBx
RBy
RBy
CBx
A0 ~ A8
RAx
RBx
CAx
DQM
DQ
Data is ignored
Hi-Z
DAx DAx+1 DAx+2
DAx+3
DAx DAx+1 DBx DBx+1
DBx+4
DBx+2 DBx+3
DBx+5
DAx-1
Activate
Command
Bank A
Activate
Write
Precharge
Command
Bank B
Activate
Command
Bank B
Write
Command
Command
Command
Bank A
Bank B
Bank B
Full Page burst operation does
not terminate when the burst
length is satisfied;the burst counter
inrements and continues bursting
beginning with the starting address.
Burst stop
Command
The burst counter wraps
from the highest order
page addresss back to zero
during this time interval
Document:
Rev.1
Page45
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
