Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
VIS
Figure 19.2 Full Page Write Cycle (Burst Length = Full Page, CAS Latency = 2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
CKE
High
CS
RAS
CAS
WE
DSF
BS
A9
RAx
RBy
RBy
RBx
RBx
A0 ~ A8
RAx
CAx
CBx
DQM
DQ
DAx DAx+1 DAx+2
Activate
DAx+3
DAx DAx+1 DBx DBx+1
DBx+3 DBx+4 DBx+5
DBx+2 DBx+6
DAx-1
Data is ignored
Precharge
Command
Bank B
Write
Command
Bank B
Activate
Command
Bank B
Write
Activate
Command
Bank A
Command
Command
Bank B
Bank A
Full Page burst operation does
not terminate when the burst
length is satisfied;the burst counter
increments and continues bursting
beginning with the starting address.
Burst Stop
Command
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Document:
Rev.1
Page44
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
