Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
VIS
Figure 19.1 Full Page Write Cycle (Burst Length = Full Page, CAS Latency = 1)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK1
CKE
High
CS
RAS
CAS
WE
DSF
BS
RAx
RAx
RBx
RBx
RBy
RBy
A9
CAx
CBx
A0 ~ A8
DQM
DQ
Hi-Z
DAx-1
DBx+4
DBx+5 DBx+6
DAx
DBx+7
DBx+3
DBx+1 DBx+2
DAx+1
DAx
DAx+3
DBx
DAx+2
DAx+1
Data is
ignored
Write
Command
Bank B
Activate
Command
Bank B
Activate
Command
Bank A
Precharge
Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Activate
Command
Bank B
Burst Stop
Command
Write
Command
Bank A
Full Page burst operation does
not terminate when the burst
length is satisfied;the burst counter
increments and continues bursting
beginning with the starting address
Document:
Rev.1
Page43
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
