Preliminary
VG37648041AT
256M:x4, x8, x16
VIS
CMOS Synchronous Dynamic RAM
BANK READ ACCESS
t
t
t
CH
CL
CK
CLK#
CLK
t
t
IS IH
CKE
VALID
t
t
IS
IH
ACT
NOP
NOP
ACT
PRE
NOP
NOP
READ
NOP
NOP
COMMAND
t
t
IH
IS
x4:A0,A9,A11
x8:A0,A9
x16:A0,A8
RA
Col n
RA
RA
x4:A12
x8:A9,A12
x16:A8,A9,A12
RA
t
t
ALL BANKS
IS IH
A10
RA
RA
ONE BANK
DIS AP
Bank x
t
t
IS IH
BA0,BA1
Bank x
*Bank x
Bank x
t
RC
t
RAS
CL=2
t
t
RCD
RP
t
t
RPR
t
RPO
t
AC
t
HZ
max
max
LZ
max
DQS
DQ
t
LZ
min
DO
N
t
t
AC
min
HZ
min
DM
DONT’ CARE
UNDEFINED
DO n=Data Out from column n
Burst Length=4 in the case shown
3 subsequent elements of Data Out are provided in the programmed order following DO n
DIS AP=Disable Autoprecharge
*=”Dont’ Care”, if A10 is HIGH at this point
PRE=PRECHARGE, ACT=ACTIVE, RA=Row Address, BA=Bank Address
NOP commands are shown for ease of illustration; other commands may be valid at these times
Document : 1G5-0157
Rev.1
Page82
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
