Preliminary
VG37648041AT
256M:x4, x8, x16
VIS
CMOS Synchronous Dynamic RAM
READ-WITH AUTO PRECHARGE
t
t
t
CH
CL
CK
CLK#
CLK
t
t
IS IH
t
IH
CKE
VALID
NOP
VALID
NOP
VALID
NOP
t
t
IS
IH
READ
NOP
NOP
NOP
NOP
PRE
ACT
RA
COMMAND
t
t
IH
IS
x4:A0,A9,A11
x8:A0,A9
Col n
x16:A0,A8
x4:A12
x8:A9,A12
x16:A8,A9,A12
RA
EN AP
A10
RA
t
t
IH
IS
Bank x
BA0,BA1
Bank x
CL=2
t
RP
t
t
RPR
t
RPO
t
AC
max
t
HZ
max
LZ
max
DQS
DQ
t
LZ
min
DO
n
t
t
AC
min
HZ
min
DM
DONT’ CARE
UNDEFINED
DO n=Data Out from column n
Burst Length=4 in the case shown
3 subsequent elements of Data Out are provided in the programmed order following DO n
EN AP=Enable Autoprecharge
ACT=ACTIVE, RA=Row Address
NOP commands are shown for ease of illustration; other commands may be valid at these times
Document : 1G5-0157
Rev.1
Page81
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
