Preliminary
VG37648041AT
256M:x4, x8, x16
VIS
CMOS Synchronous Dynamic RAM
SELF REFRESH MODE
t
CK
clock must be stable before
exiting Self Refresh mode
t
t
CH
CL
CLK#
CLK
t
t
t
t
IS
IS
IH
IS
CKE
t
t
IS
IH
COMMAND
VALID
t
NOP
AR
NOP
t
IH
IS
VALID
ADDR
DQS
DQ
DM
200 cycles
of CLK**
t
RP*
Enter
Self Refresh
Mode
EXIT
Self Refresh
Mode
DONT’ CARE
UNDEFINED
*=Device must be in the “All banks idle” state prior to entering Self Refresh mode
**=tRC is required before any command can be applied, and 200 cycles of CLK are required before a READ
command can be applied.
The minimum time in Self Refresh mode is tRAS MIN.
Document : 1G5-0157
Rev.1
Page79