Preliminary
VG37648041AT
256M:x4, x8, x16
VIS
CMOS Synchronous Dynamic RAM
INITIALIZE AND LOAD MODE REGISTERS
VDD
VDDQ
t
VTD
VTT
(system*)
VREF
t
CK
t
t
CL
CH
CLK#
CLK
t
t
IS IH
LVCMOS LOW LEVEL
CKE
NOP
PRE
LMR
PRE
LMR
ACT
COMMAND
AR
AR
DM
t
t
IS
IH
A0,A9,
A11,A12
RA
CODE
CODE
CODE
ALL BANKS
ALL BANKS
A10
CODE
RA
BA
t
t
t
t
IS
IH
IS IH
t
IS
t
IH
BA0=L,
BA1=L
BA0=H,
BA1=L
BA0,BA1
High-Z
DQS
DQ
High-Z
s
m
T=200
t
200
cycles
of CLK...
t
MRD
t
t
RP
RC
RC
Load
Extended
Mode
Register
Power-up:
VDD and
CLK stable
Load
Base
Mode
DONT’ CARE
UNDEFINED
Register
•=VTT is not applied directly to the device, however tVTD must be greater than or equal to
zero to avoid device latch-up.
••=t MRD is required before any command can be applied, and 200 cycles of CLK are required before a
READ command can be applied.
Document : 1G5-0157
Rev.1
Page76
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
