Preliminary
VG37648041AT
256M:x4, x8, x16
VIS
CMOS Synchronous Dynamic RAM
20.The minimum limit for this parameter is not a device limit. The device will operate with a negative value for
this parameter, but system performance (bus turnaround) will degrade accordingly.
21.CLK must be toggled a minimum of two times during this period.
22.The specific reguirement is that DQS be valid (HIGH or LOW) on or befor this CLK edge. The case shown
(DQS going from High-Z to logic LOW) applies when no writes were previously in progress on the bus. If
a previous write was in progress. DQS could be HIGH at this time depending on tDSS.
Document : 1G5-0157
Rev.1
Page73