Preliminary
VG37648041AT
256M:x4, x8, x16
VIS
CMOS Synchronous Dynamic RAM
A.C Characteristics:
Test Conditions: (Ta=0 to 70°C VDDQ=2.5V ±0.2V , VDD=3.3V±0.3V , or VDD=2.5V±0.2V
A.C. Parameter
Symbol
-75
-8
Unit
tCK
Note
Min.
-0.1
0.45
0.45
5
Max.
+0.1
0.55
0.55
15
Min.
-0.1
0.45
0.45
6
Max.
+0.1
0.55
0.55
15
Access time from CLK/CLK#
tAC
tCH
tCK
tCK
ns
Clock high time
Clock low time
Clock cycle time
tCL
CL=3
tCK3Q
ns
CL=2.5 tCK2.5
CL=2 tCK2
6.2
15
7
15
ns
7.5
15
8
15
ns
CL=1.5 tCK15
10
15
10
15
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ns
Data-in hold time
tDH
tDS
0.075
0.075
-0.1
-0.1
0.075
0.075
-0.1
-0.1
Data-in setup time
18
18
Data-out high imedance from CLK/CLK#
Data-out low impedance from CLK/CLK#
DQS-DQ Skew
tHZ
+0.1
+0.1
+0.1
+0.1
tLZ
tDSDQ
tDV
tDSS
tDSLH
-0.075 +0.075 -0.075
+0.075
DQ/DQS output valid time
Write command to first DQS latching transition
DQ/DQS input valid time
0.35
0.75
0.40
2
0.35
0.75
0.40
2
1.25
0.60
1.25
0.60
LOAD MODE REGISTER COMMAND cycle time
Write preamble setup time
tMRD
tWPR
tWPO
tWCP
tIH
22
19
20
0
0
Write postamble
0.4
0
0.6
0.4
0
0.6
tCK
ns
Write command to DQS Low-Z
Input hold time
0.15
0.15
0.9
0.4
45
0.15
0.15
0.9
0.4
48
tCK
tCK
tCK
tCK
ns
Input setup time
tIS
Read preamble
tRPR
tRPO
tRAS
tRC
1.1
0.6
1.1
0.6
Read postamble
ACTIVE to PRECHARGE command
AUTO REFRESH, ACTIVE command period
ACTIVE to READ or WRITE delay
Refresh period (8192 rows)
PRECHARGE command period
ACTIVE bank A to Active bank B command
Transition time
120,000
120,000
65
70
ns
tRCD
tREF
tRP
20
20
ns
64
64
ms
ns
20
15
20
20
tRRD
tT
ns
ns
Write recovery time
tWR
tWTR
tXSR
2
1
2
1
tCK
tCK
ns
Write data In to Read Command Delay
Exit SELF REFRESH to ACTIVE command
60
70
21
Document : 1G5-0157
Rev.1
Page71
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
