Preliminary
VG37648041AT
256M:x4, x8, x16
VIS
CMOS Synchronous Dynamic RAM
T0
T1
T10
T2
T3
T4
T5
T6
T7
T9
T11
T8
CLK#
CLK
COMMAND
ADDRESS
WRITE
NOP
NOP
WRITE
NOP
NOP
Bank,
Col n
Bank,
Col b
tDSS
min
DQS
DQ
Dl
n
Dl
b
DM
DONT’ CARE
UNDEFINED
Dl b, etc. = Data In for column b, etc.
3 subsequent elements of Data In are applied in the programmed order following Dl b
3 subsequent elements of Data In are applied in the programmed order following Dl n
A non-interrupted burst of 4 is shown
Each Write command may be to any bank
Figure 18
WRITE TO WRITE - MIN DSS
Document : 1G5-0157
Rev.1
Page44