Preliminary
VG37648041AT
256M:x4, x8, x16
VIS
CMOS Synchronous Dynamic RAM
T0
T1
T3
T2
T4
T5
T6
T7
T8
CLK#
CLK
COMMAND
WRITE
WRITE
WRITE
WRITE
WRITE
Bank,
Col x
Bank,
Col b
Bank,
Col a
ADDRESS
Bank,
Col g
Bank,
Col n
tDSS
min
DQS
DQ
Dl
a’
Dl
n’
Dl
a
Dl
b
Dl
x’
Dl
x
Dl
b’
Dl
n
DM
DONT’ CARE
UNDEFINED
Dl b, etc.=Data In for coulmn b, etc.
b,’etc.=odd or even complement of b, etc.(i.e. column address LSB inverted)
Programmed burst Length=2,4 or 8 in cases shown
Each Write command may be to any bank.
Figure 21
RANDOM WRITE CYCLES - MIN DSS
Document : 1G5-0157
Rev.1
Page47