Preliminary
VG36641641BT
CMOS Synchronous Dynamic RAM
VIS
8.4 Multibank Operation- Write with Auto Precharge
During a WRITEA cycle interrupted by a Read, Write command of another banks, the auto-pre-
charge scheduled time would not be changed.
Multibank Operation
Burst lengh=8
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
Auto precharge bank A starts
Command
WRITA A
Read B
CAS latency=2
Hi-Z
DB1
DB2
DB3
DQ
DB0
DA1
DB4
DA0
DB5
Auto precharge bank A starts
Command
WRITA A
Read B
CAS latency=3
Hi-Z
DB1
DB3
DB0
DB2
DA1
DB4
DQ
DA0
Multibank Operation
Burst lengh=8
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CLK
Auto precharge bank A starts
Command
WRITA A
Write B
DB0
CAS latency=2
Hi-Z
DQ
DB3
DB2
DB4
DA1
DB1
DB6
Auto precharge bank A starts
DA0
DB5
DB7
WRITA A
DA0
Write B
DB0
Command
CAS latency=3
Hi-Z
DQ
DB3
DB2
DB4
DA1
DB1
DB5
DB6
DB7
Document : 1G5-0127
Rev2
Page21
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
