Preliminary
VG36641641BT
CMOS Synchronous Dynamic RAM
VIS
8.3 Multibank Operation- Read with Auto Precharge
During a READA cycle interrupted by a Read, Write command of another banks, the auto-pre-
charge scheduled time would not be changed.
Multibank Operation
Burst lengh=8
T0
T1 T2 T3
T4 T5
T6
T7 T8
T9 T10 T11 T12 T13 T14
CLK
Auto precharge bank A starts
Command
READA A
Read B
CAS latency=2
Hi-Z
QA0
QA1
QB1
QB2
QB3
QB4
QB5
QB6
QB7
DQ
QB0
Auto precharge bank A starts
READA A
Command
Read B
CAS latency=3
Hi-Z
DQ
QA0
QA1
QB1
QB2
QB3
QB4
QB5
QB6
QB7
QB0
Similiar top.21
Document : 1G5-0127
Rev2
Page20
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
