VG3617161ET
1,048,576 x 16 - Bit
CMOS Synchronous Dynamic RAM
VIS
Precharge Termination of a Burst (2 of 2)
Burst Length=4,8 or Full Page, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK3
High
CS
RAS
CAS
WE
A11(BS)
A10
RAa
RAb
RAb
RAc
RAc
RAa
CAa
CAb
A0~A9
t
t
t
t
DPL
RAS
RP
RP
DQM
DQ
t
RCD
Hi-Z
QAb0 QAb1
QAb3
DAa0 DAa1
QAb2
Activate
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank A
Precharge
Command
Bank A
Activate
Command
Bank A
Write
Command
Bank A
Precharge Termination
of a Read Burst.
Write Data
is masked
Precharge Termination
of a Write Burst.
Document:1G5-0189
Rev.1
Page68
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
