VG3617161ET
1,048,576 x 16 - Bit
CMOS Synchronous Dynamic RAM
VIS
Full Page Write Cycle (1 of 2)
Burst Length=Full Page, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK2
High
CS
RAS
CAS
WE
A11(BS)
RAa
RBb
A10
RBa
A0~A9
CAa
CBa
RBb
RAa
RBa
DQM
DQ
t
BDL
Hi-Z
DAa+1
DBa+1 DBa+2
Write
Command
Bank B
DAa DAa+1
DAa-1 DAa
DBa
DBa+3 DBa+4 DBa+5 DBa+6
Data is ignored
DAa+2 DAa+3
Activate
Command
Bank A
Write
Activate
Command
Bank B
Activate
Command
Bank B
Precharge
Command
Bank B
Command
Bank A
Full page burst operation
The burst counter wraps
from the highest order
does not terminate when
the burst length is satisfied;
the burst counter increases
and continues bursting
beginning with the starting
address
Burst Stop
Command
page address back to zero
during this time interval
Document:1G5-0189
Rev.1
Page61
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
