VG3617161ET
1,048,576 x 16 - Bit
CMOS Synchronous Dynamic RAM
VIS
Full Page Read Cycle (2 of 2)
Burst Length=Full Page, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK3
High
CS
RAS
CAS
WE
A11(BS)
RAa
RBb
A10
RBa
A0~A9
CBa
RAa
RBa
RBb
CAa
t
RP
DQM
DQ
Hi-Z
QBa+3
QAa+1 QBa0 QBa+1 QBa+2
QAa-2
QAa QAa+1 QAa+2
QAa-1 QAa
QBa+4 QBa+5
Full page burst operation
does not teminate when
the burst length is satisfied;
the burst counter increases
and continues bursting
beginning with the starting
address
Read
Command
Bank B
Activate
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank B
Precharge
Command
Bank B
Activate
Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Burst Stop
Command
Document:1G5-0189
Rev.1
Page60