VG3617161ET
1,048,576 x 16 - Bit
CMOS Synchronous Dynamic RAM
VIS
Clock Suspension During burst Write (Using CKE) (1 of 2)
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK2
CS
RAS
CAS
WE
A11(BS)
RAa
A10
A0~A9
RAa
CAa
DQM
DQ
Hi-Z
QAa0
QAa1
QAa2
QAa3
Clock
Suspended
1 Cycle
Clock
Suspended
3 Cycles
Clock
Suspended
2 Cycles
Activate
Command
Bank A
Write
Command
Bank A
Document:1G5-0189
Rev.1
Page36