128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)
P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)
P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
AC TIMING REQUIREMENTS
(Ta=0 - 70˚C, Vdd=VddQ=3.3±0.3V,Vss=VssQ=0V, unless otherwise noted)
Input Pulse Levels:0.8V-2.0V
Input Timing Measurement Level:1.4V
Limits
-75
Unit
-7
-8
Parameter
Symbol
tCLK
Max.
Max.
Max.
Min.
Min.
Min.
-
10
10
CL=2
CL=3
ns
ns
CLK cycle time
7
8
7.5
tCH
tCL
tT
CLK High pulse width
CLK Low pulse width
2.5
2.5
2.5
2.5
3
3
ns
ns
10
10
10
1
1
1
2
ns
ns
Transition time of CLK
1.5
1.3
tIS
Input Setup time (all inputs)
0.8
0.8
tIH
Input Hold time (all inputs)
Row Cycle time
0.8
63
70
20
ns
ns
tRC
67.5
75
0
80
20
7
ns
ns
tRFC Refresh Cycle Time
tRCD Row to Column Delay
20
tRAS
Row Active time
100K
100K
100K
45
20
45
20
48
20
ns
ns
tRP
Row Precharge time
Write Recovery time
Act to Act Delay time
tWR
ns
14
14
14
15
15
15
20
20
20
tRRD
tRSC
ns
ns
Mode Register Set Cycle time
Refresh Interval time
64
64
64
ms
tREF
1.4V
1.4V
CLK
DQ
Any AC timing is referenced
to the input signal passing
through 1.4V.
JULY.2000
Rev.2.2
Page-33
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
