128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)
P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)
P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
SWITCHING CHARACTERISTICS
(Ta=0 - 70˚C, Vdd=VddQ=3.3±0.3V,Vss=VssQ=0V, unless otherwise noted)
Limits
Symbol
Parameter
-8
-7
-7.5
Unit
Note
Min.
Min.
Max.
5.4
Max.
6
Max.
Min.
CL=2
CL=3
6
6
ns
ns
tAC
tOH
Access time from CLK
5.4
3
3
CL=2
CL=3
3
3
ns
ns
Output Hold time
from CLK
*1
2.7
0
Delay time , output low-
impedance from CLK
ns
ns
tOLZ
tOHZ
NOTE:
0
3
0
3
Delay time , output high-
impedance from CLK
6
2.7
5.4
5.4
1. If clock rising time is longer than 1ns,(tr/2-0.5ns) should be added to the parameter.
Output Load Condition
CLK
1.4V
VOUT
50pF
DQ
1.4V
Output Timing Measurement
Reference Point
CLK
DQ
1.4V
1.4V
tOLZ
tAC
tOHZ
tOH
JULY.2000
Rev.2.2
Page-34
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
