128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)
P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)
P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
Multi Bank Interleaving READ (BL=4, CL=3)
CLK
Command
A0-9
ACT
Xa
READ ACT
READ PRE
Y
tRCD
Y
0
Xb
Xb
Xb
10
A10
Xa
0
0
A11
Xa
BA0,1
DQ
00
00
10
00
Qa0
Qa1 Qa2 Qa3
Burst Length
Qb0 Qb1 Qb2
/CAS latency
READ with Auto-Precharge (BL=4, CL=3)
CLK
BL + tRP
Command
A0-9
ACT
Xa
READ
ACT
Xa
tRCD
BL
tRP
Y
1
A10
Xa
Xa
A11
Xa
Xa
BA0,1
DQ
00
00
00
Qa0 Qa1
Qa2 Qa3
Internal precharge start
READ Auto-Precharge Timing (BL=4)
CLK
Command
ACT
READ
BL
Qa0
Qa1 Qa2 Qa3
CL=3 DQ
CL=2 DQ
Qa0 Qa1
Qa2 Qa3
Internal Precharge Start Timing
JULY.2000
Rev.2.2
Page-18
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
