VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC9182
64x64 STS-12/STM-4 TSI Switch Fabric
register. When the framing pattern is located in two consecutive frames, the OOF register will be set to ‘0.’ Once
in frame, if the expected 6-byte framing pattern is not found in the appropriate location for four consecutive
frames, the OOF register will be set to ‘1.’ The payload of the receive channel will be set to all ‘1’s with an A1/
A2 boundary (AIS) during OOF if OOF/LOS-AIS is not disabled via the OOF/LOS register disable bit (see
Register Map).
Outputs that are mapped to this port will receive the AIS signal in the selected time slots.
Output In-Band Signaling
The VSC9182 can send a fixed byte message from its output ports designed to signal an impending config-
uration change to the port card. The message byte and location of this byte is user programmable.
Asserting the CONFIG pin causes the byte stored in the CHANGE register to be inserted in location
CHANGE_LOC for a single frame on all outputs. This insertion takes place before scrambling and B1 calcula-
tion, but after TSI switching. Following frames transmit the byte stored in the NORMAL register until another
CONFIG signal is received. Note: In-Band Signaling overrides AIS/UNEQ for the selected byte.
Parity Checking and Insertion
System-internal parity checking is available to verify integrity of the serial links to and from the TSI. The
first B1 byte (second row, first byte position in the frame) is expected to contain the byte-interleaved parity com-
puted on the previous frame’s data (after scrambling, if used). This computation is done on-chip and compared
to the B1 byte in the following frame. If a discrepancy is found, the parity error register in that channel is set to
‘1’ and an interrupt is generated if the channel is provisioned. Reading the affected register will reset the parity
error register for that frame to ‘0’ and de-assert INTB.
The output backplane interface inserts the byte-interleaved parity computed on the previous frame’s data
(after switching and scrambling, if used) into the outgoing data at the first B1 position. This feature may be dis-
abled by tying the PRTYON pin low, which will leave the first B1 position in the outgoing data untouched.
Alternatively, parity checking can be enabled or disabled by setting the soft parity control register (see Gen-
eral Configuration Registers). Disabling parity checking requires both the PRTYON pin to be set low and the
control register be set to ‘0.’
All parity detection and generation are in conformance with ANSI T1.105, Bellcore GR-253-CORE and
ITU-T G.707 specifications.
Descrambling/Scrambling
When the SCRMBL pin is tied high, SONET descrambling is performed on the incoming data after de-seri-
alization and prior to switching. SCRMBL high also causes SONET scrambling to be performed on the outgo-
ing data after switching and before serialization. The 1 + X
6
+ X
7
polynomial is used for scrambling and
descrambling. No scrambling is performed on the first row of overhead bytes (A1, A2, J0), which corresponds
to the first 36 bytes in an OC-12 frame. The scrambling sequence is re-started on the first byte of payload fol-
lowing the unscrambled bytes and continues until the start of the next frame.
Alternatively, scrambling can be enabled or disabled by setting the soft scramble control register (see
Gen-
eral Configuration Registers).
Disabling SONET scrambling requires both the SCRMBL pin to be set low and
the control register be set to ‘0.’
All scrambling and descrambling are in conformance with ANSI T1.105, Bellcore GR-253-CORE and
ITU-T G.707 specifications.
G52289, Rev 4.1
12/6/01
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VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
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