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VSC9182UG 参数 Datasheet PDF下载

VSC9182UG图片预览
型号: VSC9182UG
PDF下载: 下载PDF文件 查看货源
内容描述: [TELECOM, DIGITAL TIME SWITCH, PBGA480, 37.50 MM, HEAT SINK, TBGA-480]
分类和应用: 电信电信集成电路
文件页数/大小: 42 页 / 456 K
品牌: VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
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VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
64x64 STS-12/STM-4 TSI Switch Fabric
VSC9182
Features Summary
Interconnection Matrix
• Time & Space Switches any STS-(n) [n= 1, 3c, 12c] signal of an incoming STS-12 into any byte position
of any STS-12 output
• Single Stage non-blocking structure of the switch allows for Multicast and Full Broadcast
• Hitless Switching: programming is queued and takes effect after user intervention during the next frame
boundary
• Unequipped or AIS signals can be substituted into any of the outgoing STS-1 time slots.
• Provides a capability to read out the switch configuration (address map)
Input Backplane Interface
• Serial 622.08Mb/s differential LVDS STS-12/STM-4 inputs
• Receives 64 serial 622.08Mb/s STS-12/STM-4 line channels (these 64 input signals are presumed fre-
quency synchronous and frame aligned to within +/- 3 time slots of the system SYNC input)
• Provides on-chip data recovery deskewing functionality to bit-align, byte-align and frame-align all
incoming STS-12s (within the above tolerance) to the local clock
• Flags Out-of-Frame (OOF), Loss-of-Signal (LOS) and parity errors
• Checks byte-interleaved parity of incoming data versus B1 byte of following frame
• Inserts unequipped or AIS when channel is in OOF, LOS or unprovisioned state and inhibits alarms
• Optionally descrambles SONET-scrambled incoming data
Output Backplane Interface
• Serial 622.08Mb/s differential LVDS STS-12/STM-4 outputs
• Optionally inserts byte-interleaved parity into B1 byte of following frame
• Optionally SONET scrambles outgoing data
• Optionally inserts AIS or unequipped on a per-channel, per-time-slot basis
CPU Interface
• Generic microprocessor (CPU) interface used for device configuration and status checking
• 10-bit data bus and 11-bit address bus
• Interrupt output pin to signal status changes of internal alarms
Test Interface
• IEEE P1149.1 test access port controls external boundary scan
Clock Synthesis PLL
• Monolithic PLL clock multiplier with 8x and 32x multiplication ratios available
Page 2
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52289, Rev 4.1
12/6/01