VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC9182
Functional Description
64x64 STS-12/STM-4 TSI Switch Fabric
Interconnection and Programming
Rearrangement in time (across time-slots) and space (across physical channels) is performed by filling the
program memory for each time-slot in each output channel with the address of the input channel and time slot
from which it will take its data (see
Internal Register Address Map).
There are 64 channels with 12 time-slots
each, for 768 possible input or output addresses. There are no restrictions on the input selected by each output.
Each output time slot may also be filled with a AIS or UNEQ signal by programming the low order D[3:0] bits
to select an internally generated bit sequence.
Programming is performed via the CPU interface port by presenting the output channel and time-slot
address on A[10:0], the input channel and time slot address on D[9:0] and pulsing WRB. A rising edge on WRB
transfers the program information to a first layer register in the program memory. The programming does not
take effect until the CONFIG pin is asserted and the next frame boundary is received (signaled by the SYNC
input). The switch may be programmed continuously but the new map will not take effect until the user asserts
the CONFIG signal. The new switch configuration is loaded and implemented within the A1/A2 boundary of
the incoming STS-12s. Since this occurs during the period where all the data contains the identical framing
bytes, no data is lost and the switching is “hitless.” The current address map may be read back by presenting the
Output channel and time-slot address on A[10:0], releasing the D[9:0] signals and lowering RDB, causing the
contents of the register to appear at D[9:0].
Note that a CONFIG signal can be generated by a rising edge on CONFIG or by writing a value ‘1’ to the
SOFTCONFIG register (A[10:0] = 7FF’h). The input pin CONFIG is logically OR’ed internally with a pulse
generator initiated by the SOFTCONFIG register.
The switch matrix reconfiguration effects of the CONFIG signal can be delayed by up to 15 frames. The
contents of the DELAY register determine the number of frames to be transmitted after receiving the CONFIG
signal before reconfiguring the switch matrix.
Functional Diagram
Time Slots In
1L
1C
2C
3C
64C
1B
2B
3B
64B
1A
CPU i/f
1B
Time Slots Out
3A
1C
3B
64C
3C
1B
1B
64B
3D
1D
4B
2C
Channels Out
Channels In
2L
3L
64L
2A
3A
64A
VSC
9182
1A
2B
64D
G52289, Rev 4.1
12/6/01
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
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