VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC9182
64x64 STS-12/STM-4 TSI Switch Fabric
Interrupt Servicing
Interrupt sequences are not accompanied by an indication of which input is causing the interrupt, therefore
it is necessary to read back all registers in order to determine the location of the fault and reset the interrupt con-
dition. An external CPU should read back the entire status register memory when an interrupt takes place.
INTB toggles low whenever a parity error register toggles high. Reading the changed register causes INTB
to return to a logic ‘1.’ Reading a parity error register resets it to ‘0.’ Writing the contents of this register has no
effect.
Interrupts can be disabled on a per channel basis. Unprovisioned inputs do not generate interrupts, and the
user can mask interrupt generation on a per channel and per alarm basis by writing the aligner register map
appropriately. Writing a ‘1’ to the D2 location of a parity status register will prevent INTB from being asserted
if there is a change of state.
While OOF and LOS interrupt generation is no longer supported, it does exist. The OOF and LOS Interrupt
Masking Status bits should be set to ‘1’ for all provisioned input channels to prevent unwanted INTB events
from occurring.
Test Access Port
The test access port provides external boundary scan capability for board-level test. The VSC9182 TAP
uses the IEEE 1149.1 standard TAP controller state machine as the interface to external boundary scan. The
TAP controller makes state transitions by sampling TMS on the rising edge of TCK. Lowering TRSTB will
place the state machine in the initial state (Test-Logic-Reset). The VSC9182 TAP implements the EXTEST,
SAMPLE/PRELOAD and BYPASS instructions. The VSC9182 TAP does not implement the optional ID Code
function. The instruction register is two bits in length, and the command codes are shown in Table 1. A scan def-
inition file may be obtained by contacting the factory. Please consult the IEEE 1149.1 for additional information
on TAP use and implementation.
Table 1: TAP Instruction Codes
Instruction Code
00
01
01, 11
Instruction
EXTEST
SAMPLE/PRELOAD
BYPASS
G52289, Rev 4.1
12/6/01
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VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
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