VSC8601 Datasheet
Pin Descriptions
6.2.2
RGMII MAC Interface
The following table lists the device pins associated with the RGMII MAC interface. Note
that the pins in this table are referenced to VDDIOMAC and can be set to a 2.5 V or
3.3 V power supply.
Table 80.
RGMII MAC Interface Pins
Pin
Name
Type
Description
20
21
22
23
RXD3
RXD2
RXD1
RXD0
OZC
Multiplexed receive data. Bits[3:0] are
synchronously output on the rising edge of
RX_CLK and bits[7:4] on the falling edge of
RX_CLK.
24
RX_CLK
OZC
Receive clock. Receive data is sourced from the
PHY synchronously on the rising edge of RX_CLK
and is the recovered clock from the media.
18
RX_CTL
OZC
Multiplexed receive data valid, receive error. This
output is sampled by the MAC on opposite edges
of RX_CLK to indicate two receive conditions from
the PHY:
1. On the rising edge of RX_CLK, this output
serves as RXDV and signals valid data is available
on the RXD input data bus.
2. On the falling edge of RX_CLK, this output
signals a receive error from the PHY, based on a
logical derivative of RXDV and RXER, as stated by
the RGMII specification.
27
28
29
30
TXD3
TXD2
TXD1
TXD0
IPD
Multiplexed transmit data. Bits[3:0] are
synchronously output on the rising edge of
TX_CLK and bits[7:4] on the falling edge of
TX_CLK.
26
TX_CLK
I
Transmit clock. This clock is 2.5 MHz for 10 Mbps
mode, 25 MHz for 100 Mbps mode, and 125 MHz
for 1000 Mbps mode. If left unconnected, these
pins require a pull-down resistor to ground.
31
TX_CTL
IPD
Multiplexed transmit enable, transmit error. This
input is sampled by the PHY on opposite edges of
TX_CLK to indicate two transmit conditions of the
MAC:
1. On the rising edge of TX_CLK, this input serves
as TXEN, indicating valid data is available on the
TXD input data bus.
2. On the falling edge of TX_CLK, this input signals
a transmit error from the MAC, based on a logical
derivative of TXEN and TXER, as stated by the
RGMII specification.
32
NSRESET
IPU
Soft Reset. Active low input that places the device
in a low-power state. Although the device is
powered down, the sticky serial management
interface registers retain their value.
Revision 4.1
September 2009
Page 86
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
