VSC8601 Datasheet
Pin Descriptions
Table 81.
SMI Pins (continued)
Pin
Name
Type
Description
10
EECLK
OZC
(Optional) EEPROM Serial Output Clock. Used to
configure PHYs in a system without a station
manager. Connect to the SCL pin of the ATMEL
“AT24CXXX” serial EEPROM device family.
8
NRESET
IPU
Device Reset. Active low input that powers down
the device and sets the register bits to their default
state.
6.2.4
JTAG
The following table lists the device pins associated with the device JTAG testing facility.
Table 82.
JTAG Pins
Pin
3
Name
TDI
Type
IPU5V
O
Description
JTAG test serial data input.
JTAG test serial data output.
JTAG test mode select.
JTAG test clock input.
2
TDO
5
TMS
IPU5V
IPU5V
IPU5V
6
TCK
7
NTRST
JTAG reset. If JTAG is not used, then tie this pin
to VSS (ground) with a pull-down resistor.
6.2.5
Miscellaneous
The following table lists the device pins associated with a particular interface or facility
on the device.
Table 83.
Miscellaneous Pins
Pin
Name
Type
Description
38
37
36
35
CMODE3
CMODE2
CMODE1
CMODE0
IA
Configuration mode (CMODE) pins. For more
information, see “CMODE,” page 64.
64
63
XTAL1/REFCLK
I
Crystal oscillator input. If OSCEN=high, then a
25 MHz parallel resonant crystal with ±50 ppm
frequency tolerance should be connected across
XTAL1 and XTAL2. A 33 pF capacitor should also tie
the XTAL1 pin to ground.
Reference clock input. If OSCEN=low, the clock input
frequency can either be 25 MHz (PLLMODE=0) or
125 MHz (PLLMODE is high).
XTAL2
OCRYST
Crystal oscillator output. The crystal should be
connected across XTAL1 and XTAL2. A 33 pF
capacitor should also tie the XTAL2 pin to ground. If
not using a crystal oscillator, this output pin can be
left floating if driving XTAL1/REFCLK with a reference
clock.
Revision 4.1
September 2009
Page 88
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
