VSC8601 Datasheet
Pin Descriptions
Table 83.
Miscellaneous Pins (continued)
Pin
Name
Type
Description
47
PLLMODE
I
PLL mode input select. Sampled on power-up or
reset. If PLLMODE is low, then REFCLK must be
25 MHz. If PLLMODE is high, then REFCLK must be
125 MHz.
If a crystal or an external 25 MHz clock is used,
PLLMODE must be pulled low. If an external 125 MHz
clock is used, PLLMODE must be pulled high.
40
41
42
LED2
LED1
LED0
O
LED direct-drive outputs. All LEDs pins are active-low.
For more information about LED operation, see “LED
Interface,” page 28.
50
49
44
REF_REXT
REF_FILT
REG_EN
ABIAS
ABIAS
I
Reference external connects to an external 2 kΩ
(1%) resistor to analog ground.
Reference filter connects to an external 1 μF capacitor
to analog ground.
Regulator enable. Active high input enables the
on-chip switching regulator and generates a 1.2 V
supply voltage.
46
REG_OUT
ABIAS
Regulator output. When REG_EN is enabled,
REG_OUT supplies a 1.2 V supply that has been
regulated from the 3.3 V supply. When connecting to
the 1.2 V supply pins, additional requirements are a
4.7 μH to 5.1 μH inductor in series as well as 10 μF
and 1 μF capacitors to ground. The on-chip switching
regulator is optional, and 1.2 V power can be
supplied externally.
48
NC
NC
No connects. Do not connect them together or to
ground. Leave these pins unconnected (floating).
6.2.6
Power Supply
The following table lists the device power supply pins.
Table 84.
Power Supply Pins
Pin
Name
Type
3.3 V
3.3 V
Description
1, 39, 51, 57, 62
VDD33
General 3.3 V supply.
45
11
VDDREG
VDDIOMICRO
On-chip switching regulator 3.3 V supply.
I/O micro power supply.
3.3 V
2.5 V
16, 19, 25, 33
VDDIOMAC
3.3 V
2.5 V
I/O MAC power supply.
4, 15, 34
52
VDD12
1.2 V
1.2 V
Internal digital core voltage.
VDD12A
1.2 V analog power requiring additional
PCB power supply filtering.
17 , PAD(1)
VSS
0 V
General device ground.
1. Exposed pad is on the bottom of the package.
Revision 4.1
September 2009
Page 89
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
