VSC8601 Datasheet
Configuration
4.2.10
1000BASE-T Status
The bits in register 10 of the main register space allow you to read the status of the
1000BASE-T communications enabled in the device. The following table lists these
readouts.
Table 18.
1000BASE-T Status, Address 10 (0x0A)
Bit
Name
Access Description
Default
15
Master/slave
configuration fault
RO
RO
This bit latches high.
1 = Master/slave configuration fault
detected.
0 = No master/slave configuration fault
detected.
0
14
Master/slave
configuration
resolution
1 = Local PHY configuration resolved to
master.
0 = Local PHY configuration resolved to
slave.
1
13
12
Local receiver status
RO
RO
1 = Local receiver okay.
1 = Remote receiver OK.
0
0
Remote receiver
status
11
10
LP 1000BASE-T FDX
capability
RO
RO
1 = LP 1000BASE-T FDX capable.
1 = LP 1000BASE-T HDX capable.
0
0
LP 1000BASE-T HDX
capability
9:8
7:0
Reserved
RO
RO
00
Idle error count
This is a self-clearing bit.
0x00
4.2.11
Main Registers Reserved Addresses
In the VSC8601 device main registers page space, registers 11 through 15 (0x0B
through 0x0E) are reserved.
4.2.12
1000BASE-T Status Extension 1
Register 15 provides additional information about the operation of the device
1000BASE-T communications. The following table lists the readouts available.
Table 19.
1000BASE-T Status Extension 1, Address 15 (0x0F)
Bit
Name
Access Description
Default
15
1000BASE-X FDX
capability
RO
RO
RO
RO
RO
1 = PHY is 1000BASE-X FDX capable
0
14
13
12
1000BASE-X HDX
capability
1 = PHY is 1000BASE-X HDX capable
1 = PHY is 1000BASE-T FDX capable
1 = PHY is 1000BASE-T HDX capable
0
1000BASE-T FDX
capability
1
1
1000BASE-T HDX
capability
11:0 Reserved
0x000
Revision 4.1
September 2009
Page 45
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